The sensor structure of such a capacitive MEMS sensor element normally includes a deflectable structured element, such as a diaphragm or a bending beam, and a stationary counter element, which are provided with an electrode of a measuring capacitor in each case. The deflectable structured element is deflected by the measured variable to be detected, e.g., the effect of force, pressure or sound, relative to the stationary counter element. The distance between the measuring capacitor electrodes changes in the process. The capacitance of the measuring capacitor changes accordingly as well. This change in capacitance forms the basis of the electrical sensor output signal.
In practice, however, the sensor output signal is defined not only by the measured variable and the geometrical and electrical characteristics of the measuring capacitor system, but also by parasitic capacitances in the layer structure of the MEMS sensor element and, in particular, by parasitic capacitances that arise between the bond pads for the electrical contacting of the measuring capacitor electrodes and further electrically conductive layers of the layer structure. Since the highest degree of linearity possible between the measured variable to be detected and the sensor output signal is desired in most sensor applications, these parasitic capacitances should be kept to a minimum.
In the Article “Design on the Low-Capacitance Bond Pad for High-Frequency I/O Circuits in CMOS Technology”, IEEE Transactions on Electron Devices, Vol. 48, No 12, December 2001, pages 2953-2956, measures aimed at reducing the parasitic capacitance between a bond pad in the bad end stack of a CMOS component and the CMOS substrate are described. Here, the bond pad is realized in the form of multiple metallization planes situated on top of one another, which are electrically interconnected via so-called via plugs. The via plugs bridge the insulation layers between the individual metallization planes, so that the bond pad structure is practically interlocked with the layer structure of the back end stack. This configuration gives the bond pad the stability and tensile strength required for the wire bonding process. The magnitude of the parasitic capacitance between such a bond pad and the CMOS substrate is essentially defined by the clearance between the substrate and the lowest metallization plane and by the area size of the lowest metallization plane, which essentially corresponds to the electrode surface of the parasitic capacitance. In the approach described here, the parasitic capacitance is to be reduced by making the electrode surface smaller. To do so, the lower metallization planes are structured, so that the excellent interlocking with the back end stack is maintained. In this case the parasitic capacitance is reduced approximately according to the functional relationship between capacitance C and electrode surface A of a plate-type capacitor.C−∈0∈r·A/d, ∈0 denoting the electrical field constant, ∈r describing the relative permittivity of the dielectric between the capacitor electrodes, and d denoting the electrode clearance.